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Synopsys, announced that the 2015.12 release of the PrimeTime static timing analysis tool provides major enhancements to address the challenges of timing and power closure for FinFET designs. New PrimeTime IoT significantly improves turnaround time (TAT) and power reduction, while providing smarter utilization of compute resources. This software release helps ensure chip designers can meet demanding signoff schedules at advanced process nodes.

“In anticipation of designers’ future timing closure challenges, Synopsys continues to offer smarter, more efficient technology,” said Robert Hoogenstryd, senior director of marketing for design analysis and signoff tools at Synopsys. “The 2015.12 release of PrimeTime keeps our customers well ahead of the curve, providing significant reduction in turnaround time without requiring them to upgrade existing hardware.”

System-on-chip (SoC) designers face pressure to close timing quickly, including reducing runtimes and finding necessary high-end compute resources. The latest release of PrimeTime takes a three-pronged approach to smarter and faster timing closure: First, it boosts performance, beginning with 2X overall faster run time and a 10X boost in reporting function speed. Second, PrimeTime provides improved scaling across 16 cores for 10-15X faster throughput compared to single core runs. Finally, tighter correlation of graph-based analysis (GBA) to path-based analysis (PBA), achieved through parametric on-chip variation (POCV) technology, means designers can spend less time doing runtime-costly PBA analysis to eliminate false violations.

“As a supplier of world-class computing solutions, our design teams must ensure our highly integrated semiconductor products achieve timing closure across a wide range of scenarios,” said Bruce Fishbein, vice president of NCD IC engineering at Cavium. “Synopsys PrimeTime’s continuously improving performance helps us meet our demanding signoff schedules.”

With its HyperScale hierarchical methodology, the 2015.12 PrimeTime release reduces the need for expensive compute assets. HyperScale provides a 5-10X improvement in TAT and memory footprint compared to flat analysis, enabling use of more available and less costly compute servers. More than 20 tapeouts have successfully taken advantage of this technology.

“Mellanox’s processing solutions excel at providing great flexibility and high performance, coupled with superior integration and power efficiency. Our engineers drive this innovation with on-time delivery of increasingly more advanced and complex designs,” said Erez Shaizaf, vice president of chip design at Mellanox. “Our ability to meet signoff targets and get analysis runs through existing server farm resources requires an efficient combination of run time and memory. PrimeTime’s HyperScale static timing analysis and ECO (engineering change order) technology delivers on both fronts.”

For mobile and IoT applications, a few extra percent of power reduction can provide significant advantages in the consumer market. New PrimeTime ECO enhancements enable designers to squeeze out an additional 5 percent power reduction, for a total power reduction of up to 40 percent. Also included is support for complex placement rules, critical to 10-nanometer (nm) FinFET, that work in tandem with Synopsys’ flagship IC Compiler™ II physical implementation tool. The PrimeTime ECO technology is deployed by more than 70 different companies over a broad set of applications.

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